1. Field of the Invention
The present invention relates to a silicon carbide semiconductor device and a method of manufacturing the silicon carbide semiconductor device.
2. Description of the Background Art
As compared to silicon (Si), a silicon carbide (hereinafter, SiC) semiconductor is generally known to have a larger breakdown electric field, band gap, and coefficient of thermal conductivity. Because of a large band gap and coefficient of thermal conductivity, a silicon carbide semiconductor has excellent heat resistance, which enables operation at high temperatures and simple cooling. Furthermore, because of a large breakdown electric field, a silicon carbide semiconductor is easily made into a thin type and has a low loss, which enables operation at high temperatures.
In the design of the SiC Schottky Barrier Diode (hereinafter, SiC-SBD) and SiC-MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), the breakdown electric field is 2.8 MV/cm when SiC is used, as compared to 0.3 MV/cm when silicon is used. If the thickness and the termination structure of the drift epitaxial layer, which is an active layer, is decided by taking advantage of this characteristic, then for example, the drift epitaxial layer may be around 1/10 of a case where silicon is used, if SiC having a breakdown electric field of approximately 10 times of silicon is used.
A kV-class high voltage SiC-SBD is configured by forming a Schottky electrode on the n-type SiC epitaxial layer.
In this structure, because an electric field can easily become concentrated on the periphery of the junction surface between the epitaxial layer and the Schottky electrode, a p-type termination structure needs to be formed for alleviating the electric field concentration, on the surface layer of the periphery of the junction surface (Schottky junction surface).
Generally, when forming the p-type termination structure, a method in which a p-type impurity, such as Al (aluminum) and B (boron), is ion-implanted into the n-type epitaxial layer, and then activation annealing is performed by high-temperature heat treatment at a temperature of 1500° C. or more, is used. Next, back polishing and back ohmic formation are performed, and a Schottky junction is formed on the surface. Additionally, aluminum of approximately 5 μm thickness is generally formed as a pad during wire bonding (WB). Conventionally, following this operation, a polyimide (hereinafter, PI) requiring cure heating of approximately 350° C. is formed as a passivation film, and finally, rear metallization of Ni/Au is performed to complete the wafer processing.
When a wafer test (hereinafter, WT) and a chip test (hereinafter, CT) need to be performed for evaluating the electrical properties of the element, then after performing WT, the element is segmented into individual chips by dicing, and CT is performed. The aforementioned one is the general process order.
The PI is formed so as to cover each of the surface electrode ends other than the surface electrode pad opening, the surface electrode end other than the dicing line opening, and the vicinity of the termination structure.
During normal PI formation, a kind of groove formation is not performed at the location corresponding to the chip end of the substrate surface, and therefore, the PI is not formed on the side walls of individual elements.
By contrast, the below-mentioned case example has been confirmed as a technique for forming a passivation film of the PI, for example, on the side walls of individual elements for any purpose.
Japanese Patent Application Laid-Open No. 2005-012206 describes a method of dividing a substrate in which a GaN crystalline layer is formed on a sapphire substrate, into chips, and more particularly describes in detail the chipping measures.
As regards the method of manufacturing the GaN element, measures against chipping in the cleavage and increased cutting amount during dicing are described. Furthermore, a process of covering the side walls inside the concave portion for electrodes with a passivation film is described.
Japanese Patent Application Laid-Open No. 2005-012206 describes that the depth of the groove that is to be formed is preferred to be 1 to 100 μm, and particularly preferred to be in the range of 1 to 50 μm, and breaking the formed groove in the end is not considered.
Japanese Patent Application Laid-Open No. 2000-183282 describes a method of simplifying the extraction of rejected chips and enabling the protection of chips during the manufacturing of modules by providing an insulating frame called a chip frame. According to the method, a smaller size and lower inductance can also be achieved.
Japanese Patent Application Laid-Open No. 2009-224641 describes a structure in which a conductor layer is formed on the entire end surface.
Japanese Patent Application Laid-Open No. 2004-064028 describes a method of forming a concave portion of 0.1 μm or more and 10 μm or less by laser scribing during the manufacturing of a silicon solar cell.
Japanese Patent Application Laid-Open No. 2006-156658 describes a structure having a concave portion on the element back surface with the purpose of reducing the on-resistance while retaining the substrate strength.
As described above, by taking advantage of the characteristic that the breakdown electric field is 2.8 MV/cm when SiC is used, as compared to the 0.3 MV/cm when silicon is used, the thickness or the termination structure of the drift epitaxial layer, which is an active layer, is decided.
When SiC having a breakdown electric field is approximately 10 times of a case where silicon is used, the drift epitaxial layer may be around 1/10 of a case where silicon is used. Even the dimension in the surface direction of the termination structure may be around 1/10 of a case where silicon is used, if an SiC material is used.
An electric discharge might occur during the evaluation of the electrical properties depending on the electric field concentration brought on as a result of the shape of the chip end, as well as the state of the chip affected by the ambient atmosphere.
Due to segmentation into individual chips, the electric discharge occurs easily in the individual elements with exposed side walls (side surfaces) on which the PI is not formed, which gives rise to the problem of occurrence of an electric discharge during CT even when the electric discharge does not occur during WT.